Polycrystalline semiconductor devices, although having poorer electrical characteristics than single crystal devices, have the attraction of being much less expensive to manufacture. The grain boundaries between crystals in a polycrystalline device constitute imperfections in the crystalline structure, and can cause increased resistivity and unwanted shunts in an electronic semiconductor device. The number of grain boundaries in a given device is a direct product of the size of the grains in the overall semiconductor body. The degrading effects of grain boundaries are pronounced when the grain boundary crosses a conductivity junction in the device.
In recent years, many methods have been investigated for improving the quality of polycrystalline semiconductors. These methods have principally focused on increasing the grain size. A semiconductor material may be seeded from the substrate through windows in an oxide coating, but this requires an expensive substrate such as sapphire or silicon. High-temperature processes such as liquid-phase crystallization can produce a single crystal structure, but require expensive substrates. Other high temperature methods include graphoepitaxy using a laser or a strip-heater oven and zone-melting.
Low-temperature methods are preferred for polycrystalline semiconductors because an inexpensive substrate, such as glass, may be used. The devices may be stacked with a new layer being fabricated over the old. With low-temperature processing, the layer underneath will not be destroyed by excessive heat. Existing low-temperature methods involve solid-phase nucleation and crystal growth. These methods result in acceptable electron channel mobilities, but the positions of the grain boundaries are not correlated with the conductivity junctions. Therefore, the devices must be much larger than the grain size in order to be well-matched.